1. Field of Invention
The present invention relates to a semiconductor integrated circuit having a plurality of circuit modules which can replace each other's functions and a method of production of the same, more particularly relates to a semiconductor integrated circuit reducing the drop in yield due to faults of circuit modules.
2. Description of the Related Art
In recent semiconductor integrated circuits, the processing dimensions are becoming increasingly finer the circuit configurations are becoming increasingly larger in scale. The drop in yield due to faults in production has become serious. Therefore, the technique of previously providing redundant circuits at parts of the overall circuit and replacing faulty portions by these redundant circuits to thereby prevent the entire semiconductor chip from being discarded as a defective product has been proposed.
In the method of generation of logical circuit data of a field programmable gate array (FPGA) disclosed in, for example, Japanese Patent No. 3491579, the need for avoiding faults is judged from fault information and logic information and, if necessary, the logic information is changed so that the function of any faulty portion is replaced by an empty portion.
In the above FPGA, where a basic unit of configuration of the logic circuit, that is, a basic cell, fails, the interconnect route is changed so as to bypass it. Detour interconnects for avoiding faults differ in accordance with the state of occurrence of the faults. It is difficult to predict in advance how the interconnect route will changed. For this reason, it is difficult to set a clear delay margin that can satisfy the desired delay conditions no matter which of the basic cells fails, so it is necessary to set a considerably large margin considering the possibility that the delay characteristic will remarkably degrade.
Further, in the semiconductor device disclosed in Japanese Patent No. 3192220, data is transferred among a plurality of circuit modules by memory map type addressing. ID codes are assigned to circuit modules. By changing the ID codes to control the destination of data, a faulty circuit module can be replaced by a redundant circuit module.
In this semiconductor device, how long the data transfer distance between circuit modules becomes may greatly vary in accordance with the state of occurrence of the faults, therefore it is necessary to prescribe the operation of each circuit module by envisioning the case where all circuit modules are separated from each other to the maximum limit. Accordingly, it is necessary to set a considerably large delay margin at the time of design and it is hard to optimize the performance of the entire system.